Electronics - Verilog - Structural description

In classic software programming there are a way to split whole code into several parts.

In Verilog there is also a technic to do the same. One calls that structural description.

It's like in C language, to talk outside the main function, it's necessary to have functions.

But the difference in this case is that parameters (ports) don't have to be called in the same order as the module requires.

Important things is that modules cannot return anything and modules are not functions, but almost.

Explanation

In the code below we are going to use module2 or module3 to call the lower-level module (module1).

We will do it with two different styles.

The first style, with module2, will use the specific fashion that Verilog can handle this type of parameters call.

Indeed, ports dont' have to be called in the exact same order as in module1.

To execute this it's necessary to put a dot before each port name and put the port argument in parenthesis.

Like this:

.input1(in1[0])

The second will use the classic way, with module3, meaning that parameters will be called in the exact order of the lower-level module.

Here no need to put a dot neither parenthesis, only the port as argument:

in1[0]

Don't forget to set module2.v as Top-Level Entity when you launch the Analysis & Synthesis and do the same for module3.v.

Then open the RTL viewer to see that there is no difference between both technics.

Code

Style 1

module1.v

// module1

module module1(

    input input0, input1,
    output output1

);
    
    assign output1 = input0 & input1;
   
endmodule

module2.v

// module2

module module2(

    input wire[1:0] in1,
    output wire[0:0] out1

);

    // call of module1
    module1 m2 (
        .input1(in1[0]),
        .output1(out1),
        .input0(in1[1])
    );
        
endmodule

Style 2

module1.v

// module1

module module1(

    input input0, input1,
    output output1

);
    
    assign output1 = input0 & input1;
   
endmodule

module3.v

// module3

module module3(

    input wire[1:0] in1,
    output wire[0:0] out1

);

    // call of module1
    module1 m3 (
        in1[0],
        in1[1],
        out1
    );
        
endmodule

Conclusion

Two ways to use modules in Verilog.

The first by calling parameters by each port name and the other by calling parameters in the exact same order as the lower-level module.

The first could be more secure if you had a lots of port to set. The second is more compact.

Good job you've made it. cool

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